• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a communication method, on a two-wire bus (5, 11), between a first circuit (1) providing a first digital signal (CLK) and a second circuit (3, 21), in which, to transmit a bit of a transmitter circuit (1; 3, 21) among the first circuit and the second circuit to the other circuit (3, 21; 1), the transmitter circuit sets a second digital signal (DATA) according to the state of the bit to be transmitted while the first signal is at a first level (GND).
    公开号:FR3036513A1
    申请号:FR1554460
    申请日:2015-05-19
    公开日:2016-11-25
    发明作者:Yvon Bahout
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    [0001] B14096 - 14-R0-0853EN01 1 COMMUNICATION METHOD ON A BIFILAR BUS Domain This application relates to data transmissions between a master circuit and a slave circuit connected on a two-wire bus.
    [0002] DESCRIPTION OF THE PRIOR ART A two-wire bus comprises a conductor carrying a data signal, and a conductor carrying a clock or synchronization signal. In a two-wire bus, the driver carrying the data signal is generally, at rest, at a potential different from the ground, generally at a positive potential such as the supply potential. The data is transmitted by pulling the driver carrying the data signal to ground according to a coding enabling the data receiver to decode the data. Many communication protocols are known operating a two-wire bus, for example type I2C protocols. In the usual systems, the different circuits connected on the two-wire bus are generally powered by one or more conductors different from those of the two-wire bus, and have a reference potential, for example the mass, common to all the circuits.
    [0003] SUMMARY An embodiment overcomes all or some of the disadvantages of known communication methods using a two-wire bus.
    [0004] An embodiment more particularly provides a communication method using a two-wire bus that is adapted to a system in which the slave circuit does not share a common potential such as ground with the master circuit. Thus, an embodiment provides a method of communicating, on a two-wire bus, between a first circuit providing a first digital signal and a second circuit, wherein, for transmitting a bit of a transmitter circuit among the first circuit and the second circuit to the other circuit, the transmitter circuit sets a second digital signal depending on the state of the bit to be transmitted while the first signal is at a first level. According to one embodiment, the bit is read on a transition of the first signal. According to one embodiment, the method further comprises a step of waking up the second circuit in which the first circuit causes a transition of a first type of the second signal while the first signal is at a second level different from the first one. level. According to one embodiment, the method further comprises a step of standby of the second circuit in which the first circuit causes a transition of a second type of the second signal while the first signal is at the second level. According to one embodiment, the transition of the first type is a falling edge and the transition of the second type is a rising edge. According to one embodiment, when transmitting a bit from the first circuit to the second circuit, while the first signal is at the first level and before positioning the second signal according to the state of the bit to be transmitted, The first circuit places the second signal at a level different from the first level. There is also provided an embodiment of a system comprising a first circuit and at least a second circuit suitable for carrying out the aforementioned communication method. According to one embodiment, the first circuit is powered by a voltage referenced to a first potential, and comprises a first switch for coupling, at the first potential, a driver of the bus carrying the second signal; the second circuit is coupled to a high potential and a low potential, and includes a second switch for coupling said conductor to the low potential; and a resistive element couples said conductor to a second potential of said voltage. According to one embodiment, the high potential and the low potential are extracted from the bus. BRIEF DESCRIPTION OF THE DRAWINGS These and other features and advantages will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying figures in which: FIG. 1 is a block diagram partial of an embodiment of a system comprising a master circuit and a slave circuit on a two-wire bus; FIG. 2 represents timing diagrams illustrating a wake-up step of the slave circuit of the system of FIG. 1; Figure 3 shows timing diagrams illustrating a transmission of the master circuit to the slave circuit of the system of Figure 1; FIG. 4 represents timing diagrams illustrating a transmission of the slave circuit to the master circuit of the system of FIG. 1; and FIG. 5 represents timing diagrams illustrating a step of putting the slave circuit of the system of FIG. 1 on standby after a transmission of the master circuit to the circuit.
    [0005] DETAILED DESCRIPTION The same elements have been designated with the same references in the various figures and, in addition, the various figures are not drawn to scale. For the sake of clarity, only the elements which are useful for understanding the described embodiments have been shown and are detailed. FIG. 1 is a partial block diagram of an embodiment of a system comprising a master circuit and a slave circuit on a two-wire bus. A master circuit 1 and a slave circuit 3 are connected by a two-wire bus. The two-wire bus comprises a conductor 5 carrying a synchronization digital signal CLK between a terminal 7 of the circuit 1 and a terminal 9 of the circuit 3. The signal CLK, supplied by the master circuit 3, is periodic or not and may have a duty cycle. and any frequency. The bus further comprises a conductor 11 conveying a digital data signal DATA between a terminal 13 of the circuit 1 and a terminal 15 of the circuit 3. The bus is bidirectional. A resistive element 16 couples the conductor 11 to a positive high potential, in this example the supply voltage VDD of the master circuit 1. The master circuit 1 comprises a terminal 17 coupled to the supply potential VDD, and a coupled terminal 18 at a GND reference potential. The slave circuit 3 comprises a voltage rectifier bridge 19, a circuit 21 for reading and possibly writing on the bus, and a capacitor 23. The rectifier bridge 19 comprises two input terminals 25 and 27 respectively coupled to the terminals 15 and 9 of the slave circuit 3, and two output terminals 29 and 31 respectively coupled to the electrodes 33 and 35 of the capacitor 23. The circuit 21 comprises two terminals 37 and 39 respectively connected to the electrodes 33 and 35 of the capacitor 3036513 B14096 - 14- R0-0853EN01 5 23, and two terminals 41 and 43 respectively coupled to terminals 9 and 15 of the circuit 3. When the signals CLK and DATA are at opposite levels, the rectifier bridge 19 provides a non-zero and positive voltage between its output terminals 31 and 29 for charging the capacitor 23. As a result, a high potential VH is available on the terminal 37 of the circuit 21, and a low potential VL is available on the terminal 39 of the circuit 21, which allows feed the circ If the slave has a battery-powered power supply 3, this is not the case. In addition, the circuit 21 of the slave circuit 3 comprises a switch 51, and the master circuit 1 comprises a switch 53. The switch 51, controlled by a signal CTRLS of the circuit 21, is used to connect the terminal 43 to the terminal 39, and the switch 53, controlled by a CTRLM signal of the circuit 1, makes it possible to couple the terminal 13 to the terminal 18. The switches 51 and 53 are, for example, made in the form of MOS transistors. At rest, the switches 51 and 53 are open and the conductor 11 is pulled at the supply potential VDD by the resistive element 16. The signal DATA is then at a high level substantially equal to the potential VDD if we neglect the fall of voltage in the resistive element 16. During transmission of a bit, at different times which depend on the communication protocol used, the conductor 11 is pulled to the reference potential GND when the switch 53 is closed, or at the low potential VI, of the terminal 39 when the switch 51 is closed and the switch 53 is open. The DATA signal is then at a low level, designated by GND / VL in the remainder of the description. In such a system, when the signals CLK and DATA are at the same level, high or low, the bridge rectifier provides no voltage. The rectifier bridge 19 therefore provides power to the circuit 21 only when the CLK and DATA signals are in opposite levels.
    [0006] According to one embodiment, provision is made for the storage or reading of a bit of the signal DATA by the receiver circuit on a rising edge of the signal CLK, the bit being the state '1' if the signal DATA is high, and the state '0' if the signal DATA is low. In addition, when reference is made to commutations of the signal DATA at the instants of the edges of the signal CLK, in practice, the level changes of the signal DATA occur at times slightly subsequent to these edges. For example, these changes in the level of the DATA signal occur after the edges of the CLK signal with a delay of the order of 1 to 10% of the duration of the CLK signal levels. FIG. 2 represents timing diagrams illustrating a wake-up step of the slave circuit. These timing diagrams 15 show the appearance of the signals CLK, CTRLs, CTRLM, and DATA. For simplicity, it is considered that the level changes of the DATA and CLK signals are instantaneous. In addition, the signals CTRLs and CTRLM are schematically represented, each CTRLs signal, CTRLM comprising a state S1 in which the corresponding switch 53, 51 is open, and a state S2 in which this switch is closed. An initial state is assumed in which the slave circuit is in standby, for example after switching on the system of FIG. 1 or after a step of putting the slave circuit into standby mode, which will be described in relation to FIG. in the wake up step, the master circuit sets the DATA signal to have a falling edge while the CLK signal is high. The initial state in which, by default, the switch 51 of the slave circuit 3 is open (CTRLs in the state S1) and the signal CLK is at a high level, substantially equal to the potential VDD, is illustrated between times t0 and tl. The state of the signal CTRLM, therefore the level of the signal DATA, is indifferent between the times t0 and t1.
    [0007] At time t1, the master circuit puts the signal CLK at a low level, substantially equal to the potential GND in this example. In addition, if the switch 53 of the master circuit is closed (CTRLM in state S2), the master circuit sets the DATA signal high by opening its switch 53 (CTRLM in state S1). At a time t3, subsequent to the next rising edge of the signal CLK (time t2), the master circuit positions the signal DATA at the low level (CTRLM in the state S2). The slave circuit sees a falling edge of the DATA signal while the CLK signal is high, and wakes up. An advantage of the wakeup step as described in connection with FIG. 2 is that the bus is read by the slave circuit in a differential manner, here at a falling edge of the DATA signal, which allows the circuit 15 slave to not share common reference potential with the master circuit. In addition, since the signals CLK and DATA are at opposite levels between the times t1 and t2, the circuit 21 is powered on the falling edge of the signal DATA at time t3.
    [0008] Figure 3 shows timing diagrams illustrating the transmission of a word, in this example a four-bit word '1', '0', '0' and '1', from the master circuit to the slave circuit. These chronograms represent, in the same way as in FIG. 2, the appearance of the signals CLK, CTRLs, CTRLM, and DATA.
    [0009] By default, the switch 51 of the slave circuit is open (CTRLs in state S1). Thus, the level of the signal DATA depends only on the state of the switch 53 of the master circuit. To transmit a bit of a word from the master circuit to the slave circuit, the master circuit sets, between two times framing a rising edge of the signal CLK, the signal DATA at a level corresponding to the state of the bit to be transmitted. The slave circuit reads the bit on this rising edge of the CLK signal. In the example shown, the successive transmission of the four bits of the master circuit to the slave circuit 35 occurs after the waking step (time t3) as described in relation to FIG. 2. The four bits of the word are read by the slave circuit at times t5, t8, t11 and t13 corresponding to four successive rising edges of the signal CLK, subsequent to the instant t3.
    [0010] At a time t4, corresponding to a falling edge of the signal CLK posterior to the instant t3 and prior to the instant t5 (rising edge of the signal CLK), the master circuit positions the signal DATA at the high level (CTRLM in FIG. S1 state) to transmit a bit to state '1'. At time t5, the slave circuit 10 reads the first bit of the signal DATA at the state '1'. The master circuit leaves its switch in the same state, here open (CTRLM in state S1), at least until the next falling edge of signal CLK (time t6). At a time t7, later than the instant t6 and prior to the instant t8 (rising edge of the signal CLK), the master circuit positions the signal DATA at the low level (CTRLM in the state S2) to transmit a bit to '0'. At time t8, the slave circuit reads the second bit of the signal DATA at the state '0'. The master circuit leaves its switch in the same state, here closed (CTRLM in state S2), to the next falling edge of signal CLK (time t9). At time t9, the master circuit sets the DATA signal high (CTRLM in state S1), opposite to the low level of signal CLK. At a time t10, later than the instant t9 and prior to the instant t11 (rising edge of the signal CLK), the master circuit positions the signal DATA at the low level (CTRLM in the state S2) to transmit a bit to state '0'. At time t11, the slave circuit reads the third bit of the signal DATA in state '0'. The master circuit leaves its switch 30 in the same state, here closed (CTRLM in state S2), to the next falling edge of signal CLK (time t12). At time t12, the master circuit sets the DATA signal high (CTRLM in state S1) to transmit a bit in state '1'. At time t13 (rising edge 30 of signal CLK), the slave circuit reads the fourth bit of signal DATA in state '1'. At the end of the transmission of the word from the master circuit to the slave circuit, the signal CLK remains high.
    [0011] An advantage of the transmission method as described in connection with FIG. 3 is that the bus is read by the slave circuit in a differential manner, here on a rising edge of the CLK signal, which allows the slave circuit not to share common reference potential with the master circuit. In addition, the signal DATA is at a level opposite to that of the signal CLK between the instants t3 and t5, t6 and t7, t8 and t10, and t11 and t13, which allows the circuit 21 of the slave circuit to be powered when reading bits on the rising edges of the CLK signal.
    [0012] In practice, in the method described with reference to FIG. 3, for the signal DATA to be correctly read, that is to say stored, by the slave circuit, the duration between the instants t7 and t8, and t10 and t11, is greater than or equal to a stabilization time of the signal DATA. This stabilization time depends on the technology used and is generally short in the time between two successive falling edges of the CLK signal. Thus, when transmitting a bit in state '0', the signals CLK and DATA are at the same level for a short time only.
    [0013] FIG. 4 shows timing diagrams illustrating the transmission of a word, in this example a four bit word '0', '1', '0' and '1', from the slave circuit to the master circuit. These chronograms represent, in the same way as in FIGS. 2 and 3, the appearance of the signals CLK, CTRLs, CTRLM, and DATA.
    [0014] To transmit a bit of a word of the slave circuit to the master circuit, the master circuit opens its switch 53 (CTRLM in the state S1) so that the level of the signal DATA depends only on the state of the signal. switch 51 of the slave circuit. The slave circuit then positions, between two successive falling edges flanking a rising edge of signal CLK, the signal DATA at a level corresponding to the state of the bit to be transmitted. The master circuit reads the bit on this rising edge of the CLK signal. In the example shown, the four bits of the word are read by the master circuit at times t15, t17, t19 and t21 corresponding to four successive rising edges of the signal CLK. At a time t14, corresponding to the falling edge of the signal CLK preceding the instant t15, the slave circuit positions the signal DATA at the low level (CTRLs in the state S2) to transmit a bit to the state '0'. At time t15 (rising edge of the signal CLK), the master circuit reads the first bit of the signal DATA at the state '0'. At a time t16, corresponding to the falling edge of the signal CLK following the instant t15 and preceding the instant t17, the slave circuit positions the signal DATA at the high level (CTRLs in the state S1) to transmit a bit to the state '1'. At time t17 (rising edge of the signal CLK), the master circuit reads the second bit of the signal DATA at the state '1'. The transmission of the third bit to state '0' between times t18 and t20, corresponding to two successive falling edges of the signal CLK surrounding time t19 (rising edge of signal CLK), is carried out in the same way as transmitting the first bit between instants t14 and t16. At time t20, prior to the rising edge of signal CLK of time t21, the slave circuit sets the DATA signal high (CTRLs in state S1) to transmit a bit in state '1'. At time t21 (rising edge of signal CLK), the master circuit reads the fourth bit of signal DATA in state '1'.
    [0015] At the end of the transmission of the slave circuit word to the master circuit, the CLK signal remains high. Because the slave circuit does not see a falling edge on the CLK signal, the DATA signal remains at the level corresponding to the state of the last bit read by the master circuit, in this example the high level.
    [0016] An advantage of the transmission method as described in connection with FIG. 4 is that, here again, the reading of the bus by the master circuit is carried out differentially. Another advantage is that the state changes of the switch 5 of the slave circuit are triggered by the level transitions of the signal CLK, which allows the synchronization signal to be supplied by the master circuit. FIG. 5 represents timing diagrams illustrating a step of putting the slave circuit on standby after the transmission of a word from the master circuit to the slave circuit. These chronograms represent, in the same way as in FIGS. 2, 3 and 4, the appearance of the signals CLK, CTRLs, CTRLM, and DATA. In the standby step, the master circuit sets the DATA signal to have a rising edge while the CLK signal is high. Here again, the reading of the bus is done in a differential way. Once the slave circuit is in standby, the slave circuit must be woken up again in accordance with the step described in connection with FIG.
    [0017] After the transmission of a word from the master circuit to the slave circuit (time t22), as described with reference to FIG. 3, the signal CLK is high, the switch of the slave circuit is open (CTRLs in the state S1) and the signal DATA is at the level corresponding to the state of the last transmitted bit. At a time t23, later than the instant t22, the master circuit positions the signal CLK at a low level. At a time t24, after t23, if the DATA signal is high, the master circuit sets the DATA signal low (CTRLM in state S2). At a time t25, later than the instant t24, the master circuit sets the signal CLK high. At a time t26, later than the instant t25, the master circuit sets the DATA signal at the high level (CTRLM in the state S1). The slave circuit sees a rising edge of the DATA signal while the CLK signal is high, and goes to sleep. Once the slave circuit is in standby and while the signal CLK is low, the master circuit can modify the level of the signal DATA to load the capacitor 23 of the slave circuit 3. In the communication method described above in connection with the 1 to 5, a bit in the '1' or '0' state is transmitted by positioning the DATA signal at the corresponding level while the CLK signal is at the low level, and the slave circuit is put on standby or woken up. causing a transition of the DATA signal while the CLK signal is high. In the above description, unless otherwise indicated, the term "substantially" means at 10% of the near VDD potential, preferably at 5% of the near VDD potential. In an exemplary application, the capacitor 23 has a value of 10 nF and the potential VDD is equal to 2.5 V. The transmission time of a byte can then be between 20 and 30 ps, for example about 26 ps. Furthermore, in this application example, between the transmission of a byte and the transmission of the next byte, the master circuit can maintain the CLK signal at a high level and the DATA signal at a low level for 5 to 15 minutes. ps, for example about 10 ps, to load the capacity. There is then an average transmission rate of between 250 and 300 kbits.s-1, for example 270 kbits.s-1. Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, although a communication method has been described in which the reading of a bit takes place on a rising edge of the signal CLK, this method also applies in the case where the reading of a bit on a falling edge of the CLK signal. In this case, a bit in state '1' or 35 '0' is transmitted by positioning the signal DATA at the corresponding level while the signal CLK is at the high level, and the circuit slave is put on standby or woken up by causing a DATA signal transition while the CLK signal is low. Likewise, the wake up and sleep steps have been described with falling edges and respective amounts of the DATA signal. This method also applies in the case where the waking and standby steps are performed with rising and falling edges of the DATA signal.
    [0018] It has previously been indicated that a bit is in the state '1' when the signal DATA is at a high level, and at the state '0' when the signal DATA is at a low level. This coding can be reversed. In addition, although four or eight bit word transmissions have been described, the communication method applies to the transmission of a single bit or words having any number of bits. Although a system comprising only a single slave circuit has been shown in FIG. 1, the person skilled in the art can apply the communication method described above to a system comprising several slave circuits, for example by combining the method of communication with known addressing protocols of the slave circuits. Moreover, although a system has been described in which the driver of the bus carrying the data signal DATA is at a high level at rest, the communication method also applies in the case where this driver is at a level low at rest. Furthermore, the transmission, wake-up and standby methods also apply in the case where the voltage rectifier bridge is of the simple alternating type, and in the case where the slave circuit 3 comprises a power supply battery type rather than a bridge rectifier associated with a capacity. Finally, certain steps of the communication method also apply in the case where the bus is unidirectional.
    权利要求:
    Claims (9)
    [0001]
    REVENDICATIONS1. A method of communicating, on a two-wire bus (5, 11), between a first circuit (1) providing a first digital signal (CLK) and a second circuit (3, 21), in which, for transmitting a bit of a circuit transmitter (1; 3, 21) among the first circuit and the second circuit to the other circuit (3, 21; 1), the transmitter circuit positions a second digital signal (DATA) according to the state of the bit to be transmitted while the first signal is at a first level (GND).
    [0002]
    The communication method according to claim 1, wherein the bit is read on a transition of the first signal (CLK).
    [0003]
    The method of claim 1 or 2, further comprising a step of waking up the second circuit (3, 21) in which the first circuit (1) causes a transition of a first type of the second signal (DATA). while the first signal (CLK) is at a second level (VDD) different from the first level (GND).
    [0004]
    4. The communication method as claimed in claim 3, further comprising a step of stopping the second circuit (3, 21) in which the first circuit (1) causes a transition of a second type of the second signal ( DATA) while the first signal (CLK) is at the second level (VDD).
    [0005]
    The communication method according to claim 4, wherein the transition of the first type is a falling edge and the transition of the second type is a rising edge.
    [0006]
    The communication method according to any of claims 1 to 5, wherein, when transmitting a bit of the first circuit (1) to the second circuit (3, 21), while the first signal ( CLK) is at the first level (GND) and before positioning the second signal (DATA) according to the state of the bit to be transmitted, the first circuit positions the second signal at a level (VDD) different from the first level. 3036513 B14096 - 14-R0-0853EN01
    [0007]
    7. System comprising a first circuit (1) and at least one second circuit (3, 21) adapted to the implementation of the communication method according to any one of claims 1 to 6. 5
    [0008]
    8. System according to claim 7, wherein: the first circuit (1) is supplied with a voltage referenced to a first potential (GND), and comprises a first switch (53) for coupling, at the first potential, a conductor (5); ) of the bus carrying the second signal (DATA); The second circuit (3, 21) is coupled to a high potential (VH) and a low potential (VL), and comprises a second switch (51) for coupling said conductor (5) to the low potential; and a resistive element (16) couples said conductor (5) to a second potential (VDD) of said voltage.
    [0009]
    9. System according to claim 8, wherein the high potential (VH) and the low potential (VL) are extracted from the bus.
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    公开号 | 公开日
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    CN205356296U|2016-06-29|
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    法律状态:
    2016-04-21| PLFP| Fee payment|Year of fee payment: 2 |
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    2017-04-21| PLFP| Fee payment|Year of fee payment: 3 |
    2018-04-23| PLFP| Fee payment|Year of fee payment: 4 |
    2019-04-19| PLFP| Fee payment|Year of fee payment: 5 |
    2021-02-12| ST| Notification of lapse|Effective date: 20210105 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1554460|2015-05-19|
    FR1554460A|FR3036513B1|2015-05-19|2015-05-19|COMMUNICATION METHOD ON A BIFILAR BUS|FR1554460A| FR3036513B1|2015-05-19|2015-05-19|COMMUNICATION METHOD ON A BIFILAR BUS|
    CN201510845796.5A| CN106169929B|2015-05-19|2015-11-26|Pass through the method for the communication of dual-wire bus|
    CN201520965585.0U| CN205356296U|2015-05-19|2015-11-26|Circuit system , main circuit and follow circuit|
    US14/984,073| US10135625B2|2015-05-19|2015-12-30|Method of communication over a two-wire bus|
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